Virtual ground EPROM arrays are known in the art. Also known are alternating metal virtual ground EPROM arrays, described in U.S. Pat. Nos. 5,151,375 and 5,204,835, assigned to the common assignees of the present invention.
In the Background of the '375 and '835 patents, it is noted that the general trend in the EPROM industry is to reduce the size of each EPROM cell in the array. This has been done in a number of ways: by reducing the "design rule", (i.e. the minimum width of features on the lithographic masks used to produce the shapes of the integrated circuit elements) and by changing the architecture to one which utilizes less space. The design rule is determined by the capabilities of the lithographic processes with which the EPROM array is produced.
In general, an architecture usually can only be produced in a few different size design rules. For each architecture, there is usually one or two design rules any smaller than which the EPROM array cannot economically be produced, either due to poor resulting yields or to manufacturing expense.
The ideal architecture would be one all of whose elements are dependent only on the design rule. Such an architecture would reduce in size as the design rule decreases in size, without approaching a limit. One version of the ideal architecture is known as a "poly pitch limited" architecture whose size is a function of the pitch of lines of polycrystalline silicon (polysilicon or "poly") used to create an EPROM cell. The basic EPROM cell is detailed in FIG. 1, to which reference is now made.
An EPROM array 10 comprises two polysilicon layers, called "poly 1" and "poly 2". The polysilicon layers are produced on a semiconductor substrate (not shown) in a grid having intersecting lines 30 of poly 1 and lines 32 of poly 2. Parallel, spaced apart doped regions 34, known as diffusion bit lines, are formed in the silicon substrate between and in alignment with the poly 1 lines 30.
The area around an "intersection" of a poly 1 line 30 and a poly 2 line 32 is an EPROM transistor or cell 12, wherein the portion of the poly 1 line 30 beneath the poly 2 line 32 is a floating gate of the EPROM transistor 12.
In an ideal cell 12, the width of each poly 1 and poly 2 line is L, where L is the design rule, and the space between the lines is D. A typical value for L in a 0.8 .mu.m technology is 0.8 .mu.m. The area of the EPROM cells 12 is then (L+D).sup.2 where L+D is known as the "pitch" of each line. If L and D are equal, which is the ideal, then the area is 4 L.sup.2. A cell 12 having an area of 4 L.sup.2 is "poly pitch limited" in that it depends only on the pitch of the poly lines 30 and 32.
The alternating metal virtual ground EPROM array described in U.S. Pat. Nos. 5,151,375 and 5,204,835 is generally, though not completely, a poly pitch limited architecture. The teachings of U.S. Pat. Nos. 5,151,375 and 5,204,835 are incorporated herein by reference. With reference to FIG. 2, the following is a brief discussion of the alternating metal virtual ground architecture and operation.
The EPROM array of U.S. Pat. Nos. 5,151,375 and 5,204,835 comprises an EPROM area 10 comprising a plurality of EPROM transistors 12, or cells, surrounded by two "control areas" 14 comprising control elements, detailed hereinbelow.
In the EPROM area 10, each cell 12 comprises a gate 16, a source 18 and a drain 20. The sources 18 of a column of EPROM cells 12 together form non-metal-strapped, segmented diffusion bit lines, labeled S-1, S and S+1. The drains 20 of a column of EPROM cells 12 together form metal-strapped, continuous diffusion bit lines labeled M-1, M and M+1. Segmented bit lines S-1, S and S+1 typically connect together N EPROM cells 12, where N is typically 64. The gates 16 of a row of cells are connected to one word line WLi.
Each control area 14 comprises select transistors 22, contacts 26 and select lines SELn and SEL(n+1). Select transistors 22 are typically stacked gate transistors but can also be n-channel devices. One contact 26 is connected to each bit line M-1, M or M+1 in each control area 14.
A pair of select transistors 22 from two neighboring control areas 14 are operative, when activated by the appropriate select lines SELn or SEL(n+1), to connect one segmented diffusion bit line S-1, S or S+1 to a neighboring continuous diffusion bit line M-1, M or M+1.
In order to access the EPROM cell labeled 12a, the following lines are activated: word line WL1, select lines SEL(n+1) and bit lines M and M-1. Bit line M receives the drain voltage and bit line M-1 receives the source voltage. The select transistors 22 which are activated by select lines SEL(n+1) transfer the source voltage from bit line M-1 to the segment S-1. Word line WL1 activates a row of EPROM cells and bit lines M and M-1 activate a column of cells, thereby activating only EPROM cell 12a, which sits at the intersection of the activated row and column. The output of the EPROM cell 12a is provided through the contact 26 which is connected to the appropriate bit line.
In order to ensure that the current only flows between the strapped and non-strapped bit lines M and S-1, respectively, through selected EPROM cell 12a, neighboring select transistors 22 are isolated from each other. This is illustrated in FIG. 2 by spaces 24 which, in reality, are field oxide isolation units 24 (shown in FIG. 3A). Units 24 isolate the select transistors 22 from each other such that no current flows between them.
Unfortunately, the isolation units 24 are not poly pitch limited, as shown in FIGS. 3A and 3B to which reference is now made. FIGS. 3A and 3B are schematic cross-sectional views of one area 14 having a few isolation units 24 and select transistors 22.
The transistors 22 and isolation units 24 have very similar structures. Each comprise a strip 40 of poly 1, of width L, covered by a strip of poly 2, labeled 42. They each also typically comprise sandwich layers 41, located between the two poly layers, and side oxides 43. Each sandwich layer 41 comprises a poly-poly dielectric formed of an oxide-nitride-oxide (ONO) dielectric layer capped by a polysilicon and a nitride layer.
In the select transistors 22, the poly 1 strip 40 lies on a thin, gate oxide strip 44 laid on top of a semiconductor substrate 46 (the "wafer") formed of silicon. When the select transistor 22 is active, current flows through an area 45 under the gate oxide strip 44, known as the "channel".
In the isolation units 24, the poly 1 strip lies on top of a very thick, field oxide element 48, typically of a thickness of 5000 .ANG. or greater. This thickness is large enough to ensure that the isolation unit 24 generally does not leak current.
As can be seen, each field oxide element 48 is not completely coincident with its corresponding strip 40 of poly 1. In fact, the field oxide elements 48 extend beyond the poly 1 strips 40. These extensions are known as "oxide beaks", labeled 50, and their size varies with manufacturing variations. The oxide beaks 50 extend into the area of the bit lines and reduce their width. The remaining portions of diffusion bit lines are labeled 52.
The isolation units 24 are not poly pitch limited for at least two reasons, as described hereinbelow.
Firstly, in order to ensure complete isolation, the minimum feature width Q of the field oxide element layer 48 is typically wider than the poly width L. Additionally, the oxide beaks 50 extend beyond the minimum feature width Q, by an imprecisely controllable distance.
Secondly, the mask used to produce the poly 1 strips 40 is often misaligned with the mask used to produce the field oxide elements 48, causing the poly 1 strips 40 to be misplaced vis-a-vis the field oxide elements 48. The resultant cross-section is illustrated in FIG. 3B, wherein a poly 1 strip 40a is too close to a field oxide element 48a.
If poly 1 strip 40a is very close to field oxide element 48a, the material (typically arsenic) used to implant the bit line diffusions 52 will not reach the silicon of the wafer 46 and the bit line diffusion 52, in the area of the field oxide element 48a, will have a discontinuity. Therefore, no bit line diffusion 52 is shown between strip 40a and field oxide element 48a. The resultant select transistor 22 fails to electrically connect the metal-strapped bit line (M) to its neighboring segmented bit line (S).
If the space between poly 1 strip 40a and field oxide element 48a is such that some arsenic, but not enough, succeeds in implanting, the bit line diffusion 52 will be too narrow and will have a high resistance. The signal from a select transistor 22 having such a bit line will be weak during reading and the rate of programming will be slow.
Therefore, in the prior art, when determining a distance J between strips 40 of poly 1, the following was considered: a minimal spacing SPACE between the field oxide element 48 and the adjacent poly 1 strip 40 necessary to ensure successful implantation of the bit line diffusion 52, the expected size BEAK of the oxide beak, the expected variation OXIDE in the size of the oxide beak 50, the expected extent MISALIGN of the misalignment, and the expected variation ETCH in the width of the poly 1 caused by the poly 1 etch. The distance J is given as: EQU J&gt;SPACE+BEAK+sqrt(OXIDE.sup.2 +MISALIGN.sup.2 +ETCH.sup.2) (1)
where "sqrt" indicates the square root function. Table 1 lists the variables of equation for the 0.8 .mu.m process such as is described in U.S. Pat. No. 5,151,375 and for a smaller 0.5 .mu.m process. The value of J provided is the minimal value of J.
TABLE 1 ______________________________________ VALUES FOR VARIABLES OF EQUATION 1 (in .mu.m) 0.8 .mu.m 0.5 .mu.m Variable process process ______________________________________ SPACE 0.35 0.3 BEAK 0.35 0.25 OXIDE 0.1 0.05 MISALIGN 0.3 0.2 ETCH 0.1 0.05 Minimum J 1.03 0.76 Ideal Cell Size 2.56 1.0 Actual Width Between 1.0 0.6 Cells Actual Cell Size 3.25 1.39 Percentage Increase 27% 39% Between Ideal and Actual Pitch ______________________________________
For an 0.8 .mu.m process, a J of 1.03 .mu.m is only 27% larger than the desired poly pitch of 0.8 .mu.m. However, for a 0.5 .mu.m process, a J of 0.76 .mu.m is an unacceptable increase of 39%. For the 0.5 .mu.m process, J is still large because, although the design rule for lithographic processes is less, the values for BEAK, OXIDE, MISALIGN and ETCH are not reduced accordingly. As can be seen, the variables BEAK, OXIDE, MISALIGN and ETCH limit the extent to which any design can truly become poly pitch limited.
It will be appreciated that the pitch of the cell along a row (the X pitch) is the same as the size required for the control area 14. Thus, the cell ceases to be poly pitch limited.